環宇翔
博士，研究員，研究組組長
Email: yxhuan@@gdiist.cn
個人簡介：
環宇翔，研究員，類腦計算架構與超大規模處理系統研究組組長，類腦計算系統研究中心主任。曾于復旦大學取得微電子學與固體電子學博士學位，先后任復旦大學信息科學與工程學院任助理研究員、廣東省智能科學與技術研究院副研究員、研究員。環宇翔博士長期圍繞領域專用處理架構（Domain-Specific Architecture, DSA）的芯片系統設計和領域應用開展研究，重點聚焦于從芯片到系統的分布式互聯處理架構和設計方法的研究，包括可重構可擴展架構的領域專用處理器、深度學習模型的高能效加速和分布式處理、神經擬態專用集成電路和超大規模類腦計算系統等。環宇翔博士在智能院工作期間，帶領團隊完成了超大規模類腦原型驗證系統的研制、多尺度可擴展的類腦智能計算芯片研制。其主持和參與了多項國家級和省部級項目，已累計發表學術論文40余篇，申請發明專利20余項。
類腦計算架構與超大規模處理系統課題組：
本課題組主要面向類腦計算的硬件處理架構和超大規模類腦計算系統設計展開研究，旨在借鑒人腦的信息處理機制，設計具有神經擬態特性的專用處理內核、大規模的芯片互聯架構與方法、以及面向全腦尺度千億神經元規模超級計算系統。課題組將主要聚焦：面向類腦計算的領域專用處理架構與芯片設計，超低延時和高可靠的片上網絡互聯，面向晶圓級集成芯片的新型片上分布式處理架構和任務調度方法。目標通過“算法-架構-電路”協同設計的方法，實現事件驅動的超大規模芯片計算網絡，支持海量處理內核的局部數據共享、異步信息傳遞和分布式協同處理，最終支撐千億神經元規模的類腦計算系統的設計構建。
本課題組面向（智能計算芯片架構設計、智能算法編譯優化方向、并行計算軟硬件協同優化等方向）招聘博士后、工程師、實習生，感興趣的同學，請郵件聯系。
代表論著：
[1] J. Xu, J.Fan, B. Nan, C. Ding, L. Zheng, Z. Zou, Y. Huan*, "ASLog: An Area-Efficient CNN Accelerator for Per-Channel Logarithmic Post-Training Quantization," in IEEE Transactions on Circuits and Systems I: Regular Papers, 2023. (SCI，通信作者)
[2] H. Jia#, Y. Huan#*; C. Ding, Y. Yan, J. Cui, J. Wang, C. Cai, L. Xu, Z. Zou*, L. Zheng*, "ASLog: An Area-Efficient CNN Accelerator for Per-Channel Logarithmic Post-Training Quantization," in IEEE Transactions on Industrial Informatics, 2022. (SCI，共同一作，共同通信作者)
[3] C. Ding#, Y. Huan#*, H. Jia, Y. Yan, F. Yang, L. Liu, M. Shen, Z. Zou and L.R. Zheng, "A Hybrid-Mode On-Chip Router for the Large-Scale FPGA-Based Neuromorphic Platform," in IEEE Transactions on Circuits and Systems I: Regular Papers, 2022. (SCI，共同一作，共同通信作者)
[4] B. Huang#, Y. Huan#*, H. Jia, C. Ding, Y. Yan, B. Huang, L.R. Zheng, and Z. Zou, "AIOC: An All-In-One-Card Hardware Design for Financial Market Trading System," in IEEE Transactions on Circuits and Systems II: Express Briefs, 2022. (SCI，共同一作，共同通信作者)
[5] Y. Jin, B. Huang, Y. Yan; Y. Huan*, J. Xu, S. Li, P. Gope, L. Xu, Z. Zou, and L.R. Zheng, "Edge-based Collaborative Training System for Artificial Intelligence-of-Things," in IEEE Transactions on Industrial Informatics, 2022. (SCI，共同通信作者）
[6] B. Huang#, Y. Huan#*, H. Chu, J. Xu, L.R. Zheng, and Z. Zou, “IECA: An In-Execution Configuration CNN Accelerator With 30.55 GOPS/mm2 Area Efficiency,” in IEEE Transactions on Circuits and Systems I: Regular Papers, 2021. (SCI，共同一作，通信作者)
[7] J. Xu#, Y. Huan#, B. Huang, H. Chu, Y. Jin, L.R. Zheng, Z. Zou, “A Memory-Efficient CNN Accelerator Using Segmented Logarithmic Quantization and Multi-Cluster Architecture,” in IEEE Transactions on Circuits and Systems II: Express Briefs, 2020. (SCI，共同一作)
[8] Y. Huan, N. Ma, J. Mao, S. Blixt, Z. Lu, Z. Zou and L. R. Zheng, “A 101.4 GOPS/W Reconfigurable and Scalable Control-Centric Embedded Processor for Domain-Specific Applications,” in IEEE Transactions on Circuits and Systems I: Regular Papers, 2016. (SCI)
[9] Y. Jin, J. Cai, J. Xu, Y. Huan*, Y. Yan, B. Huang, Y. Guo, L.R. Zheng, Z. Zou, “Self-aware distributed deep learning framework for heterogeneous IoT edge devices,” Future Generation Computer Systems, 2021. (SCI，通信作者)
[10] W. Li, H. Chu, B. Huang, Y. Huan*, L.R. Zheng, Z. Zou, “Enabling on-device classification of ECG with compressed learning for health IoT,” Microelectronics Journal, 2021. (SCI，通信作者)
[11] J. Xu#, Y. Huan#, B. Huang, H. Chu, Y. Jin, L.R. Zheng, Z. Zou, “Base-Reconfigurable Segmented Logarithmic Quantization and Hardware Design for Deep Neural Networks,” in Journal of Signal Processing Systems, 2020. (SCI，共同一作)
[12] Y. Huan, J. Xu, L. Zheng, H. Tenhunen and Z. Zou, “A 3D Tiled Low Power Accelerator for Convolutional Neural Network,” 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018. (EI)
